LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 265

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.9.5
31:30
28:16
BITS
15:0
29
RESERVED
General Purpose Timer Enable (TIMER_EN)
This bit enables the GPT. When set, the GPT enters the run state. When
cleared, the GPT is halted. On the 1 to 0 transition of this bit, the
GPT_LOAD field of this register will be preset to FFFFh.
0: GPT Disabled
1: GPT Enabled
RESERVED
General Purpose TImer Pre-Load (GPT_LOAD)
This value is pre-loaded into the GPT. This is the starting value of the GPT.
The timer will begin decrementing from this value when enabled.
General Purpose Timer Configuration Register (GPT_CFG)
This read/write register configures the LAN9312 General Purpose Timer (GPT). The GPT can be
configured to generate host interrupts at the interval defined in this register. The current value of the
GPT can be monitored via the
12.1, "General Purpose Timer," on page 161
Offset:
08Ch
DESCRIPTION
General Purpose Timer Count Register
DATASHEET
265
for additional information.
Size:
32 bits
(GPT_CNT). Refer to
TYPE
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
FFFFh
0b
-
-
Section