LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 410

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.5.4
14.5.4.1
BITS
31:7
4:2
6
5
1
0
RESERVED
BM Counter Test
When this bit is set, Buffer Manager (BM) counters that normally clear to 0
when read, will be set to 7FFF_FFFC when read.
Fixed Priority Queue Servicing
When set, output queues are serviced with a fixed priority ordering. When
cleared, output queues are serviced with a weighted round robin ordering.
Egress Rate Enable
When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
Drop on Yellow
When this bit is set, packets that exceed the Ingress Committed Burst Size
(colored Yellow) are subjected to random discard.
Note:
Drop on Red
When this bit is set, packets that exceed the Ingress Excess Burst Size
(colored Red) are discarded.
Note:
Buffer Manager CSRs
This section details the Buffer Manager (BM) registers. These registers allow configuration and
monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their
corresponding register numbers is included in
Buffer Manager Configuration Register (BM_CFG)
This register enables egress rate pacing and ingress rate discarding.
See
Register (SWE_INGRSS_RATE_CMD)," on page 393
information on configuring the Ingress Committed Burst Size.
See
Register (SWE_INGRSS_RATE_CMD)," on page 393
information on configuring the Ingress Excess Burst Size.
Register #:
Section 14.5.3.26, "Switch Engine Ingress Rate Command
Section 14.5.3.26, "Switch Engine Ingress Rate Command
1C00h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
410
Table
Size:
14.12.
for
for
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
RO
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
0b
-