LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 117

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
Reserved
FIELD
FIELD
30:0
2:1
31
3
0
Filter 3 Offset
The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether
or not this is a wake-up frame.
The Filter i command register controls Filter i operation.
DESCRIPTION
Must be zero (0)
Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset
+ j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored.
DESCRIPTION
Address Type: Defines the destination address type of the pattern. When bit is set, the pattern
applies only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.
RESERVED
Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.
Command
Filter 3
Filter 1 CRC-16
Filter 3 CRC-16
Table 9.2 Wake-Up Frame Filter Register Structure
Reserved
Table 9.3 Filter i Byte Mask Bit Definitions
Table 9.4 Filter i Command Bit Definitions
Filter 2 Offset
FILTER I BYTE MASK DESCRIPTION
Command
Table
FILTER i COMMANDS
Filter 2
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
DATASHEET
9.3, describes the byte mask’s bit fields.
117
Reserved
Filter 1Offset
Table 9.4
Command
Filter 1
Filter 0 CRC-16
Filter 2 CRC-16
shows the Filter i command register.
Reserved
Filter 0 Offset
Revision 1.7 (06-29-10)
Command
Filter 0