LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 275

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.3.4
BITS
31:0
Upper 32-bits of the 64-bit Hash Table
Host MAC Multicast Hash Table High Register (HMAC_HASHH)
The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the
destination address in the incoming frame is used to index the contents of the Hash table. The most
significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit
within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value
of 11111 selects the Bit 31 of the Multicast Hash Table Hi register.
If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All
Multicast” (MCPAS) bit of the
accepted regardless of the multicast hash values.
The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast
Hash Table Low register contains the lower 32 bits of the hash table. Refer to
Filtering," on page 114
This table determines if the Host MAC accepts the packets from the switch fabric. The switch fabric
address table and configuration determine the packets that get sent to the Host MAC.
Offset:
for more information on address filtering.
4h
DESCRIPTION
Host MAC Control Register (HMAC_CR)
DATASHEET
275
Size:
32 bits
is set, then all multicast frames are
TYPE
R/W
Section 9.4, "Address
Revision 1.7 (06-29-10)
00000000h
DEFAULT