LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 239

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.6.7
BITS
31:0
Physical Address[31:0]
This field contains the lower 32-bits (31:0) of the physical address of the
Switch Fabric MACs.
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This
r e g i s t e r i s u s e d i n c o n j u n c t i o n w i t h
(SWITCH_MAC_ADDRH). The contents of this register are optionally loaded from the EEPROM at
power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most significant byte
(bits [31:24]) is loaded from address 04h of the EEPROM. These EEPROM values are also loaded
into the
field after the initialization process has completed.
Refer to
this register. Refer to
EEPROM Loader.
Host MAC Address Low Register
Offset:
Section 9.6, "Host MAC Address," on page 119
Section 10.2.4, "EEPROM Loader," on page 149
1F4h
DESCRIPTION
DATASHEET
239
(HMAC_ADDRL). The Host can update the contents of this
S w i t c h F a b r i c M A C A d d r e s s H i g h R e g i s t e r
Size:
for details on how the EEPROM Loader loads
32 bits
for information on using the
TYPE
R/W
Revision 1.7 (06-29-10)
FF0F8000h
DEFAULT