LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 448

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
15.5.7
SYMBOL
FIFO_SEL
END_SEL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
D[31:0]
ah
A[2]
RX Data FIFO Direct PIO Burst Read Cycle Timing
Please refer to
description of this mode.
Note: A RX Data FIFO direct PIO burst read cycle begins when both nCS and nRD are asserted.
Note:
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values
The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and
de-asserted in any order.
Fresh data is supplied each time A[2] toggles.
Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
t
asu
Section 8.4.7, "RX Data FIFO Direct PIO Burst Reads," on page 109
t
don
t
acyc
t
csdv
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
t
adv
t
acyc
448
t
adv
MIN
13
45
0
0
0
0
t
adv
t
acyc
t
ah
TYP
t
doh
t
doff
t
MAX
csh
30
40
9
for a functional
SMSC LAN9312
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS