LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 109

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
8.4.7
D[31:0] (OUTPUT)
FIFO_SEL
END_SEL
nCS, nRD
A[x:3]
RX Data FIFO Direct PIO Burst Reads
In this mode only A[2] is decoded, and any burst read of the LAN9312 will read the RX Data FIFO.
This mode is enabled when FIFO_SEL is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful
when the host processor must increment its address when accessing the LAN9312. Timing is identical
to a PIO burst read, and the FIFO_SEL and END_SEL signals have the same timing characteristics
as the address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD read
cycles. RX Data FIFO direct PIO burst reads can be performed using chip select (nCS) or read enable
(nRD). An RX Data FIFO direct PIO burst read begins when both nCS and nRD are asserted. Either
or both of these control signals must de-assert between bursts for the period specified in
“RX Data FIFO Direct PIO Burst Read Cycle Timing Values,” on page
either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
Read data is valid as indicated in the functional timing diagram in
Note: Fresh data is supplied each time A[2] toggles.
Please refer to
the AC timing specifications for PIO RX Data FIFO direct PIO burst read operations.
Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation
A[2]
Section 15.5.7, "RX Data FIFO Direct PIO Burst Read Cycle Timing," on page 448
(READ DATA FROM RX DATA FIFO)
DATASHEET
109
Figure
448. The burst cycle ends when
8.6.
Revision 1.7 (06-29-10)
Table 15.11,
for