LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 445

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
15.5.4
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
A[x:2], END_SEL
t
csh
asu
don
doff
doh
csl
ah
nCS, nRD
PIO Read Cycle Timing
Please refer to
Note: A host PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
D[31:0]
either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted
in any order.
Section 8.4.4, "PIO Reads," on page 106
Table 15.8 PIO Read Cycle Timing Values
DESCRIPTION
Figure 15.4 PIO Read Cycle Timing
t
asu
DATASHEET
t
don
t
csdv
445
t
csl
t
for a functional description of this mode.
cycle
t
doh
MIN
45
32
13
0
0
0
0
t
ah
TYP
t
t
doff
csh
Revision 1.7 (06-29-10)
MAX
30
9
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS