LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 270

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.3.1
30:24
BITS
31
23
22
21
20
19
18
17
Receive All Mode (RXALL)
When set, all incoming packets will be received and passed on to the
address filtering function for processing of the selected filtering mode on the
received frame. Address filtering then occurs and is reported in Receive
Status. When cleared, only frames that pass Destination Address filtering
will be sent to the application.
RESERVED
Disable Receive Own (RCVOWN)
When set, the Host MAC disables the reception of frames when TXEN (bit
3) is asserted. The Host MAC blocks the transmitted frame on the receive
path. When cleared, the Host MAC receives all packets, including those
transmitted by the Host MAC. This bit should be cleared when the Full
Duplex Mode bit is set.
RESERVED
Loopback operation Mode (LOOPBK)
Selects the loop back operation modes for the Host MAC. This field is only
valid for full duplex mode. In internal loopback mode, the TX frame is
received by the internal MII interface, and sent back to the Host MAC
without being sent to the switch fabric.
0: Normal Operation. Loopback disabled.
1: Loopback enabled
Note:
Full Duplex Mode (FDPX)
When set, the Host MAC operates in Full-Duplex mode, in which it can
transmit and receive simultaneously.
Pass All Multicast (MCPAS)
When set, indicates that all incoming frames with a Multicast destination
address (first bit in the destination address field is 1) are received. Incoming
frames with physical address (Individual Address/Unicast) destinations are
filtered and received only if the address matches the Host MAC Address.
Promiscuous Mode (PRMS)
When set, indicates that any incoming frame is received regardless of its
destination address.
Inverse filtering (INVFILT)
When set, the address check function operates in inverse filtering mode.
This is valid only during Perfect filtering mode. Refer to
"Inverse Filtering," on page 116
Host MAC Control Register (HMAC_CR)
This read/write register establishes the RX and TX operation modes and controls for address filtering
and packet filtering. Refer to
Bits 19-15, 13, and 11 determine if the Host MAC accepts the packets from the switch fabric. The
switch fabric address table and configuration determine which packets get sent to the Host MAC.
When enabling or disabling the loopback mode it can take up to
10 μ s for the mode change to occur. The transmitter and receiver
must be stopped and disabled when modifying the LOOPBK bit.
The transmitter or receiver should not be enabled within10 μ s of
modifying the LOOPBK bit.
Offset:
1h
DESCRIPTION
Chapter 9, "Host MAC," on page 112
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
for additional information.
DATASHEET
270
Size:
Section 9.4.4,
32 bits
for additional information.
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
0b
1b
0b
-
-