LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 157

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
11.2.1
Clock synchronization and hardware processing between the network data and the time stamp capture
hardware causes the time stamp point to be slightly delayed. The host software can account for this
delay, as it is fairly deterministic.
mode of operation. Refer to
Once the packet type is matched, according to
verified, the following occurs:
Note: Packets that do not contain an integral number of octets are not considered valid and do not
Capture Locking
The corresponding ports’ clock capture, sequence ID, and source UUID registers can be optionally
locked when a capture event occurs, preventing them from being overwritten until the host clears the
corresponding interrupt flag in the
This is accomplished by setting the corresponding lock enable bit(s) in the
(1588_CONFIG). Each port has two lock enable control bits within this register, which allow the receive
and transmit portions of each port to be locked independently. In addition, a lock enable bit is provided
for each time stamp enabled GPIO (LOCK_ENABLE_GPIO_8 and LOCK_ENABLE_GPIO_9) which
prevents the corresponding GPIO clock capture registers from being overwritten when the GPIO
interrupt in
14.2.5.22, "1588 Configuration Register (1588_CONFIG)," on page 222
the capture locking related bits.
MODE OF OPERATION
The time stamp is loaded into the corresponding ports’ capture registers:
The Sequence ID and Source UUID are loaded into the corresponding ports’ registers:
The corresponding maskable interrupt flag is set in the
(1588_INT_STS_EN). (Refer to
on IEEE 1588 interrupts.)
–On Reception:
–On Transmission:
–On Reception:
–On Transmission:
(1588_CLOCK_HI_RX_CAPTURE_x)
Register (1588_CLOCK_LO_RX_CAPTURE_x)
(1588_CLOCK_HI_TX_CAPTURE_x)
Register (1588_CLOCK_LO_TX_CAPTURE_x)
(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)
DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)
Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)
Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)
cause a capture.
100 Mbps
10 Mbps
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
Port x 1588 Clock High-DWORD Receive Capture Register
Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register
Port x 1588 Clock High-DWORD Transmit Capture Register
Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture
Table 11.2 Time Stamp Capture Delay
Chapter 7, "Ethernet PHYs," on page 82
Table 11.2
1588 Interrupt Status and Enable Register
DATASHEET
Section 11.6, "IEEE 1588 Interrupts," on page 160
157
details the time stamp capture delay as a function of the
and
and
Table
Port x 1588 Clock Low-DWORD Transmit Capture
Port x 1588 Clock Low-DWORD Receive Capture
11.1, and the Frame Check Sequence (FCS) is
and
1588 Interrupt Status and Enable Register
Port x 1588 Source UUID Low-
DELAY (+/- 10 nS)
and
120 nS
30 nS
for details on these modes.
Port x 1588 Source UUID
for additional information on
1588 Configuration Register
(1588_INT_STS_EN).
is set. Refer to
Revision 1.7 (06-29-10)
for information
Section