LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 258

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.43 The default value of this field is the result of the Auto-Negotiation process if the
Note 14.44 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via
Note 14.45 The default value of this field is determined via the SQE_test_disable_strap_mii
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
N e g o t i a t i o n ( V P H Y _ A N )
(VPHY_BASIC_CTRL)
(VPHY_SPEED_SEL_LSB)
VPHY_BASIC_CTRL register. Refer to
page 96
the
(PMT_CTRL). The NASR designation is only applicable when the
of the
configuration strap. Refer to
additional information.
Reset Control Register (RESET_CTL)
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
for information on the Auto-Negotiation determination process of the Virtual PHY.
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
is set. Otherwise, this field reflects the
and
258
b i t o f t h e
Section 4.2.4, "Configuration Straps," on page 40
Duplex Mode (VPHY_DUPLEX)
Section 7.3.1, "Virtual PHY Auto-Negotiation," on
V i r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
or
Power Management Control Register
is set.
Reset (VPHY_RST)
Speed Select LSB
bit settings of the
SMSC LAN9312
Datasheet
Auto-
for
bit