LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 346

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 1.7 (06-29-10)
14.5.2.25
BITS
31:0
TX Deferred
Count of packets that were available for transmission but were deferred on
the first transmit attempt due to network traffic (either on receive or prior
transmission). This counter is not incremented on collisions. This counter is
incremented only in half-duplex operation.
Note:
Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)
This register provides a counter deferred packets. The counter is cleared upon being read.
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
Register #:
Port0: 0451h
Port1: 0851h
Port2: 0C51h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
346
Size:
32 bits
TYPE
RC
SMSC LAN9312
00000000h
DEFAULT
Datasheet