LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 169

• Manufacturer Part Number: LAN9312-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9312-NZW

• Lead Free Status / RoHS Status: Supplier Unconfirmed

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
0B0h - 0FCh
Access Only
Access Only
ADDRESS
OFFSET
EEPROM
EEPROM
Loader
Loader
0ACh
09Ch
0A0h
0A4h
0A4h
0A8h
0A8h
10Ch
12Ch
100h
104h
108h
110h
114h
118h
120h
124h
128h
130h
134h
138h
11C
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2
1588_SRC_UUID_LO_RX_CAPTURE_1
1588_SRC_UUID_LO_RX_CAPTURE_2
1588_SRC_UUID_LO_TX_CAPTURE_1
1588_CLOCK_LO_RX_CAPTURE_1
1588_CLOCK_LO_RX_CAPTURE_2
1588_CLOCK_LO_TX_CAPTURE_1
1588_CLOCK_LO_TX_CAPTURE_2
1588_CLOCK_HI_RX_CAPTURE_1
1588_CLOCK_HI_RX_CAPTURE_2
1588_CLOCK_HI_TX_CAPTURE_1
1588_CLOCK_HI_TX_CAPTURE_2
Table 14.1 System Control and Status Registers (continued)
MAC_CSR_DATA
MAC_CSR_CMD
PMI_ACCESS
RESERVED
FREE_RUN
SYMBOL
RX_DROP
PMI_DATA
AFC_CFG
DATASHEET
169
Free Running Counter Register,
Host MAC RX Dropped Frames Counter Register,
Section 14.2.2.6
Host MAC CSR Interface Command Register,
Section 14.2.2.7
PHY Management Interface Data Register (EEPROM
Loader Access Only),
Host MAC CSR Interface Data Register,
PHY Management Interface Access Register (EEPROM
Loader Access Only),
Host MAC Automatic Flow Control Configuration Register,
Section 14.2.2.9
Reserved for Future Use
Port 1 1588 Clock High-DWORD Receive Capture
Register,
Port 1 1588 Clock Low-DWORD Receive Capture Register,
Section 14.2.5.2
Port 1 1588 Sequence ID, Source UUID High-WORD
Receive Capture Register,
Port 1 1588 Source UUID Low-DWORD Receive Capture
Register,
Port 1 1588 Clock High-DWORD Transmit Capture
Register,
Port 1 1588 Clock Low-DWORD Transmit Capture
Register,
Port 1 1588 Sequence ID, Source UUID High-WORD
Transmit Capture Register,
Port 1 1588 Source UUID Low-DWORD Transmit Capture
Register,
Port 2 1588 Clock High-DWORD Receive Capture
Register,
Port 2 1588 Clock Low-DWORD Receive Capture Register,
Section 14.2.5.2
Port 2 1588 Sequence ID, Source UUID High-WORD
Receive Capture Register,
Port 2 1588 Source UUID Low-DWORD Receive Capture
Register,
Port 2 1588 Clock High-DWORD Transmit Capture
Register,
Port 2 1588 Clock Low-DWORD Transmit Capture
Register,
Port 2 1588 Sequence ID, Source UUID High-WORD
Transmit Capture Register,
Section 14.2.5.1
Section 14.2.5.4
Section 14.2.5.5
Section 14.2.5.6
Section 14.2.5.8
Section 14.2.5.1
Section 14.2.5.4
Section 14.2.5.5
Section 14.2.5.6
REGISTER NAME
Section 14.2.7.1
Section 14.2.7.2
Section 14.2.5.3
Section 14.2.5.3
Section 14.2.5.7
Section 14.2.5.7
Section 14.2.9.7
Revision 1.7 (06-29-10)
Section 14.2.2.8