NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 102

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

5.1.5
Table 5-2.
Note:
5.1.6
Note:
102
Peer Cycles
The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and
configuration cycle types. Peer cycles are only allowed through VC0, and are enabled
with the following bits:
When enabled for peer for one of the above cycle types, the PCI bridge will perform a
peer decode to see if a peer agent can receive the cycle. When not enabled, memory
cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles
are not claimed.
Configuration cycles have special considerations. Under the PCI Local Bus Specification,
these cycles are not allowed to be forwarded upstream through a bridge. However, to
enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are
allowed into the part. The address format of the type 1 cycle is slightly different from a
standard PCI configuration cycle to allow addressing of extended PCI space. The format
is as follows:
Type 1 Address Format
The ICH7’s AC ’97, IDE and USB controllers cannot perform peer-to-peer traffic.
PCI-to-PCI Bridge Model
From a software perspective, the ICH7 contains a PCI-to-PCI bridge. This bridge
connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH7
can have its decode ranges programmed by existing plug-and-play software such that
PCI ranges do not conflict with graphics aperture ranges in the Host controller.
All downstream devices should be disabled before reconfiguring the PCI Bridge. Failure
to do so may cause undefined results.
31:27
26:24
23:16
15:11
10:8
7:2
1
0
• BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and IO cycles
• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles
Bits
Reserved (same as the PCI Local Bus Specification)
Extended Configuration Address – allows addressing of up to 4K. These
bits are combined with bits 7:2 to get the full register.
Bus Number (same as the PCI Local Bus Specification)
Device Number (same as the PCI Local Bus Specification)
Function Number (same as the PCI Local Bus Specification)
Register (same as the PCI Local Bus Specification)
0
Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.
Definition
Intel
®
ICH7 Family Datasheet
Functional Description