NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 266

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

7.1.3
7.1.4
7.1.5
266
VCAP2—Virtual Channel Capability #2 Register
Offset Address: 0008–000Bh
Default Value:
PVC—Port Virtual Channel Control Register
Offset Address: 000C–000Dh
Default Value:
PVS—Port Virtual Channel Status Register
Offset Address: 000E–000Fh
Default Value:
31:24
15:04
15:01
23:8
7:0
3:1
Bit
Bit
Bit
0
0
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present
for VC arbitration since it is fixed.
Reserved
VC Arbitration Capability (AC) — RO. This field indicates that the VC arbitration is
fixed in the root complex. VC1 is highest priority and VC0 is lowest priority.
Reserved
VC Arbitration Select (AS) — RO. This field indicates which VC should be programmed
in the VC arbitration table. The root complex takes no action on the setting of this
field since there is no arbitration table.
Load VC Arbitration Table (LAT) — RO. This bit indicates that the table programmed
should be loaded into the VC arbitration table. This bit is defined as read/write with
always returning 0 on reads.
Reserved
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the
VC Arbitration table when it is being updated. This field is always 0 in the root
complex since there is no VC arbitration table.
00000001h
0000h
0000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
Intel
RO
32-bit
R/W, RO
16-bit
RO
16-bit
®
ICH7 Family Datasheet