NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 428

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

10.8.1.9
428
EL_CNT1—Intel
D31:F0) (ICH7DH Only)
Offset Address: B1h-B2h
Default Value:
Power Well:
15:10
5:4
3:2
Bit
9
8
7
6
1
0
Reserved
SMI_OPTION_CNT—R/W:
0 = Disable. Platform does Not generate an SMI when an Intel Quick Resume
1 = Enable. Platform generates an SMI when an Intel QRT event occurs (rather than
SCI_NOW_CNT—WO: When software writes a 1 to this bit, it causes
EL_SCI_NOW_STS (Offset B0:Bit 4) to assert (which can be enabled to cause an SCI).
This allows the SMI handler to cause the SCI.
PWRBTN_INT_EN—R/W:
0 = Disable.
1 = Enable. The Intel QRT logic is enabled to intercept the power button to cause the
NOTE: This bit is effective only in S0.
PWRBTN_EVNT—WO: When this bit is set to 1 by software, the PWRBTN_STS bit is
set to 1. This allows software to communicate PWR_BTN event to OS.
NOTES:
1.
2.
EL_STATE1_CNT[1:0]—R/W: These bits controls the EL_STATE1 pin. The
EL_STATE[1:0] pins can be used to control a multi color LED to indicate the platform
power states to user. If EL_LED_OWN is 0 then these bits have no impact.
00 = Low
01 = High
10 = Blinking. Note that the blink rate is ~ 1 Hz
11 = Reserved. Software must not set this combination
EL_STATE0_CNT[1:0]—R/W: These bits controls the EL_STATE0 pin. The
EL_STATE[1:0] pins can be used to control a multi-color LED to indicate the platform
power states to user. If EL_LED_OWN is 0 then these bits have no impact.
00 = Low
01 = High
10 = Blinking. Note that the blink rate is ~ 1 Hz
11 = Reserved. Software must not set this combination
EL_LED_OWN—R/W: Software sets this bit to 1 to configure the multiplexed pins to
be EL_STATE[1:0] rather than GPIO[28:27].
Reserved
Technology (QRT) event occurs
generating an SCI). The SMI handler can cause the SCI by setting the
SCI_NOW_CNT.
Intel QRT SMI or SCI, and not immediately setting the PWRBTN_STS bit. The Intel
QRT software will later set the PWRBTN_STS bit by setting the PWRBTN_EVNT bit.
Power Button override still possible
Software does not need to clear this bit, as it is treated as an event
F000h
Resume
®
Quick Resume Technology Control 1 Register (PM—
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W, RO, WO
16-bit
®
ICH7 Family Datasheet