NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 628

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

16.1.18
16.1.19
16.1.20
628
INT_PN—Interrupt Pin Register (Audio—D30:F2)
Address Offset: 3Dh
Default Value:
Lockable:
This register indicates which PCI interrupt pin is used for the AC '97 module interrupt.
The AC '97 interrupt is internally OR’d to the interrupt controller with the PIRQB#
signal.
PCID—Programmable Codec Identification Register
(Audio—D30:F2)
Address Offset: 40h
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3
register must be modified before any AC ’97 codec accesses.
CFG—Configuration Register (Audio—D30:F2)
Address Offset: 41h
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O
accesses. This register is not affected by the D3
7:0
7:4
3:2
1:0
Bit
Bit
7:1
Bit
0
AC '97 Interrupt Routing — RO. This reflects the value of D30IP.AAIP in chipset
configuration space.
Reserved.
Tertiary Codec ID (TID) — R/W. These bits define the encoded ID that is used to
address the tertiary codec I/O space. Bit 1 is the first bit sent and Bit 0 is the second bit
sent on ACZ_SDOUT during slot 0.
Secondary Codec ID (SCID) — R/W. These two bits define the encoded ID that is
used to address the secondary codec I/O space. The two bits are the ID that will be
placed on slot 0, bits 0 and 1, upon an I/O access to the secondary codec. Bit 1 is the
first bit sent and bit 0 is the second bit sent on ACZ_SDOUT during slot 0.
Reserved—RO.
I/O Space Enable (IOSE) — R/W.
0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h
1 = Enable.
become read only registers. Additionally, bit 0 of the I/O BARs at offsets 10h and
14h are hardwired to 0 when this bit is 0. This is the default state for the I/O BARs.
BIOS must explicitly set this bit to allow a legacy driver to work.
See Description
No
09h
No
00h
No
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
HOT
HOT
to D0 transition. The value in this
to D0 transition.
Intel
RO
8 bits
Core
R/W
8 bits
Core
R/W
8 bits
Core
®
ICH7 Family Datasheet