NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 205

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
Figure 5-10. USB Legacy Keyboard Flow Diagram
Table 5-47. USB Legacy Keyboard State Transitions (Sheet 1 of 2)
Intel
®
ICH7 Family Datasheet
GateState1
Current
State
IDLE
IDLE
IDLE
IDLE
IDLE
KBC Accesses
PCI Config
Read, Write
USB_IRQ
Clear USB_IRQ
64h / Write
64h / Write
60h / Write
60h / Write
64h / Read
60h / Read
Action
Decoder
Comb.
EN_SMI_ON_IRQ
EN_PIRQD#
Don't Care
Not D1h
60 READ
Clear SMI_60_R
Value
Data
D1h
XXh
N/A
N/A
S
R
D
EN_SMI_ON_60R
GateState1
GateState2
State
Next
IDLE
IDLE
IDLE
IDLE
Same for 60W, 64R, 64W
S
R
AND
AND
D
Standard D1 command. Cycle passed
through to 8042. SMI# doesn't go active.
PSTATE (offset C0, bit 6) goes to 1.
Bit 3 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
Bit 2 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
Bit 1 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
Bit 0 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
Cycle passed through to 8042, even if trap
enabled in Bit 1 in Config Register. No SMI#
generated. PSTATE remains 1. If data value
is not DFh or DDh then the 8042 may chose
to ignore it.
AND
Comment
To "Caused By" Bit
To PIRQD#
To Individual
"Caused By"
"Bits"
OR
SMI
205