NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 418
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
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10.8
10.8.1
Table 10-9. Power Management PCI Register Address Map (PM—D31:F0)
418
Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicate, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
Power Management PCI Configuration Registers
(PM—D31:F0)
Table 10-9
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
B1h-B2h
B8–BBh
Offset
ADh
A0h
A2h
A4h
ABh
B0h
B3h
AAh
A9h
shows a small part of the configuration space for PCI Device 31: Function 0.
C4-TIMING_CNT
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
Cx-STATE_CNF
BM_BREAK_EN
Mnemonic
GPI_ROUT
EL_CNTL1
EL_CNTL2
MSC_FUN
EL_STS
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
Cx State Configuration (Mobile/Ultra
Mobile Only).
C4 Timing Control (Mobile/Ultra Mobile
Only).
BM_BREAK_EN
Miscellaneous Functionality
Intel
Register (Digital Home Only)
Intel Quick Resume Technology Control 1
Register (Digital Home Only)
Intel Quick Resume Technology Control 2
Register (Digital Home Only)
GPI Route Control
®
Quick Resume Technology Status
Register Name
LPC Interface Bridge Registers (D31:F0)
Intel
®
0000000
ICH7 Family Datasheet
Default
0000h
F000h
00h
00h
00h
00h
00h
00h
00h
00h
0h
R/WC, RO
R/W, RO,
R/W, RO,
R/W, RO
R/W, R/
R/W, R/
R/WO
Type
R/W
R/W
R/W
R/W
R/W
WO
WC
WC
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