NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 768

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

21.1.2
768
SPIC—SPI Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 02h
Default Value:
13:8
6:4
Bit
15
14
7
3
2
1
0
SPI SMI# Enable — R/W.
0 = Disable.
1 = Enable. The SPI asserts an SMI# request when the Cycle Done Status bit is 1.
DATA Cycle— R/W.
0 = No data is delivered for this cycle, and the DBC and data fields themselves are
1 = There is data that corresponds to this transaction.
Data Byte Count (DBC) — R/W. This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in decimal) are any
value from 0 to 63. The number of bytes transferred is the value of this field plus 1.
For example, when this field is 000000b, then there is 1 byte to transfer and that
111111b means there are 64 bytes to transfer.
Reserved
Cycle Opcode Pointer — R/W. This field selects one of the programmed opcodes in
the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic
Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer — R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. By
making this programmable, the Intel
opcodes for enabling writes to the data space vs. status register
0 = A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes
Atomic Cycle Sequence (ACS) — R/W.
0 = No atomic cycle sequence.
1 = When set to 1 along with the SCGO assertion, the ICH7 will execute a sequence of
SPI Cycle Go (SCGO) — R/W. This bit always returns 0 on reads.
0 = SPI cycle Not started.
1 = A write to this register with a 1 in this bit starts the SPI cycle defined by the other
NOTE: Writes to this bit while the Cycle In Progress bit is set are ignored.
NOTE: Other bits in this register can be programmed for the same transaction when
SPI Access Request — R/W. This bit is used by software to request that the other SPI
master stop initiating long transactions on the SPI bus.
0 = No request.
1 = Request that the other SPI master stop initiating long transactions on the SPI bus.
NOTE: This bit defaults to a 1 and must be cleared by BIOS after completing the
don't cares.
register.
commands on the SPI interface without allowing the LAN component to arbitrate
and interleave cycles.
bits of this register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action.
writing this bit to 1.
accesses for the boot process.
4005h
Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
®
Description
ICH7 supports flash devices that have different
Size:
Attribute:
Intel
R/W
16 bits
®
ICH7 Family Datasheet