NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 671

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.12
18.1.13
Intel
®
ICH7 Family Datasheet
BNUM—Bus Number Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 18–1Ah
Default Value:
IOBL—I/O Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Ch–1Dh
Default Value:
23:16
15:12
15:8
11:8
7:0
7:4
3:0
Bit
Bit
Subordinate Bus Number (SBBN) — R/W. This field indicates the highest PCI bus
number below the bridge.
Secondary Bus Number (SCBN) — R/W. This field indicates the bus number the
port.
Primary Bus Number (PBN) — R/W. This field indicates the bus number of the
backbone.
I/O Limit Address (IOLA) — R/W. This field contains the I/O Base bits
corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be
padded to FFFh.
I/O Limit Address Capability (IOLC) — R/O. This field indicates that the bridge does not
support 32-bit I/O addressing.
I/O Base Address (IOBA) — R/W. This field contains the I/O Base bits
corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be
padded to 000h.
I/O Base Address Capability (IOBC) — R/O. This field indicates that the bridge does not
support 32-bit I/O addressing.
000000h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
24 bits
R/W, RO
16 bits
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