NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 503
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.24
Note:
Intel
®
ICH7 Family Datasheet
SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2)
Address Offset: 4Ah
Default Value:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation, unless otherwise noted.
15:14
13:12
11:10
9:8
7:6
Bit
Reserved
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of
these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these bits.
Reserved
Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of
these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these bits.
Reserved
SCB1 = 0 (33 MHz clk)
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6
01 = CT 3 clocks, RP 5
10 = CT 2 clocks, RP 4
00 = CT 4 clocks, RP 6
01 = CT 3 clocks, RP 5
10 = CT 2 clocks, RP 4
11 = Reserved
11 = Reserved
0000h
clocks
clocks
clocks
clocks
clocks
clocks
–
4Bh
SCB1 = 1 (66 MHz clk)
SCB1 = 1 (66 MHz clk)
01 = CT 3 clocks, RP 8
10 = CT 2 clocks, RP 8
01 = CT 3 clocks, RP 8
10 = CT 2 clocks, RP 8
00 = Reserved
11 = Reserved
00 = Reserved
11 = Reserved
Description
clocks
clocks
clocks
clocks
Attribute:
Size:
01 = CT 3 clocks, RP 16
01 = CT 3 clocks, RP 16
R/W
16 bits
FAST_SCB1 = 1
FAST_SCB1 = 1
(133 MHz clk)
(133 MHz clk)
00 = Reserved
10 = Reserved
11 = Reserved
00 = Reserved
10 = Reserved
11 = Reserved
clocks
clocks
503
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