NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 740
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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19.2.14
740
INTSTS—Interrupt Status Register
(Intel
Memory Address:HDBAR + 24h
Default Value:
29:8
7:0
Bit
31
30
Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in
this register.
NOTE: This bit is not affected by the D3
Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.
0 = An interrupt condition did Not occur as described below.
1 = An interrupt condition occurred due to a Response Interrupt, a Response Buffer
NOTES:
1.
2.
Reserved
Stream Interrupt Status (SIS) — RO.
0 = An interrupt condition did Not occur on the corresponding stream.
1 = An interrupt condition occurred on the corresponding stream. This bit is an OR of all
NOTE: These bits are set regardless of the state of the corresponding interrupt enable
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
®
High Definition Audio Controller—D27:F0)
Overrun Interrupt, or a SDIN State Change event. The exact cause can be
determined by interrogating other registers. This bit is an OR of all of the stated
interrupt status bits for this register.
of the stream’s interrupt status bits.
This bit is set regardless of the state of the corresponding interrupt enable bit,
but a hardware interrupt will not be generated unless the corresponding enable
bit is set.
This bit is not affected by the D3
bits.
00000000h
Intel® High Definition Audio Controller Registers (D27:F0)
Description
HOT
HOT
Attribute:
Size:
to D0 transition.
to D0 transition.
Intel
RO
32 bits
®
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