NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 412

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

10.6.2.2
412
RTC_REGB—Register B (General Configuration)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
Bit
7
6
5
4
3
Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not
affected by RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update cycles will not occur until
NOTE: This bit should be set then cleared early in BIOS POST after each powerup
Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on
any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register
Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any
other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the
Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but
not on any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
Square Wave Enable (SQWE) — R/W. This bit serves no function in the Intel
It is left in this register bank to provide compatibility with the Motorola 146818B. The
ICH7 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.
SET is returned to 0. When set is one, the BIOS may initialize time and calendar
bytes safely.
A.
update cycle. An alarm can occur once a second, one an hour, once a day, or one a
month.
directly after coin-cell battery insertion.
0Bh
U0U00UUU (U: Undefined) Size:
No
Description
Attribute:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Intel
R/W
8-bit
RTC
®
ICH7 Family Datasheet
®
ICH7.