NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 313
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.23
Intel
®
ICH7 Family Datasheet
PMCSR — Power Management Control/
Status Register (LAN Controller—B1:D8:F0)
Offset Address: E0h
Default Value:
14:13
12:9
7:5
3:2
1:0
Bit
15
8
4
PME Status (PME_STAT) — R/WC.
0 = Software clears this bit by writing a 1 to it. This also deasserts the PME# signal and
1 = Set upon occurrence of a wake-up event, independent of the state of the PME
Data Scale (DSCALE) — RO. This field indicates the data register scaling factor. It
equals 10b for registers 0 through 8 and 00b for registers nine through fifteen, as
selected by the “Data Select” field.
Data Select (DSEL) — R/W. This field is used to select which data is reported through
the Data register and Data Scale field.
PME Enable (PME_EN) — R/W. This bit enables the Intel
controller to assert PME#.
0 = The device will not assert PME#.
1 = Enable PME# assertion when PME Status is set.
Reserved
Dynamic Data (DYN_DAT) — RO. Hardwired to 0 to indicate that the device does not
support the ability to monitor the power consumption dynamically.
Reserved
Power State (PWR_ST) — R/W. This 2-bit field is used to determine the current
power state of the integrated LAN controller, and to put it into a new power state. The
definition of the field values is as follows:
00 = D0
01 = D1
10 = D2
11 = D3
clears the PME status bit in the Power Management Driver Register. When the
PME# signal is enabled, the PME# signal reflects the state of the PME status bit.
enable bit.
0000h
–
E1h
Description
Attribute:
Size:
®
RO, R/W, R/WC
16 bits
ICH7’s integrated LAN
313
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