NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 471

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

UHCI Controllers Registers
11.1.4
Note:
11.1.5
Intel
®
ICH7 Family Datasheet
PCISTS—PCI Status Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
RID—Revision Identification Register
(USB—D29:F0/F1/F2/F3)
Offset Address: 08h
Default Value:
10:9
7:0
2:0
Bit
Bit
15
14
13
12
11
8
7
6
5
4
3
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register.
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when a data parity error data parity error is detected on writes to the UHCI
Reserved as 0b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = No master abort generated by USB.
1 = USB, as a master, generated a master abort.
Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
0 = Intel
1 = USB function is targeted with a transaction that the ICH7 terminates with a target
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for
DEVSEL# assertion. These read only bits indicate the ICH7's DEVSEL# timing when
performing a positive decode. ICH7 generates DEVSEL# with medium timing for USB.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable — RO. Hardwired to 0.
Capabilities List — RO. Hardwired to 0.
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
Reserved
register space or on read completions returned to the host controller.
abort.
®
See bit description
ICH7 did Not terminate transaction for USB function with a target abort.
06h
0280h
–
07h
®
Description
Description
I/O Controller Hub 7 (ICH7) Family Specification
Attribute:
Size:
Attribute:
Size:
R/WC, RO
16 bits
RO
8 bits
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