NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 350

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

9.1.7
9.1.8
9.1.9
350
PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh
Default Value:
HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh
Default Value:
BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18h-1Ah
Default Value:
23:16
15:8
6:0
7:0
7:3
2:0
Bit
Bit
Bit
7
Multi-Function Device (MFD) — RO. The value reported here depends upon the state
of the AC ‘97 function hide (FD) register (Chipset Config Registers:Offset 3418h), per
the following table:
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge in this case.
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number
below the bridge.
Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.
Primary Bus Number (PBN) — RO. Hardwired to 00h for legacy software compatibility.
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base
Specification, Revision 1.0a.
Reserved
FD.AAD
0
0
1
1
00h
81h
000000h
FD.AMD
0
1
0
1
MFD
1
1
1
0
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
Intel
RO
8 bits
RO
8 bits
R/W, RO
24 bits
®
ICH7 Family Datasheet