NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 604

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

15.1.6
15.1.7
15.1.8
15.1.9
604
PI—Programming Interface Register (IDE—D31:F1)
Address Offset: 09h
Default Value:
SCC—Sub Class Code Register (IDE—D31:F1)
Address Offset: 0Ah
Default Value:
BCC—Base Class Code Register (IDE—D31:F1)
Address Offset: 0Bh
Default Value:
CLS—Cache Line Size Register (IDE—D31:F1)
Address Offset: 0Ch
Default Value:
6:4
7:0
Bit
Bit
7:0
7:0
Bit
Bit
7
3
2
1
0
This read-only bit is a 1 to indicate that the Intel
Reserved. Hardwired to 000b.
SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary
controller supports both legacy and native modes.
SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary
IDE channel is operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller
supports both legacy and native modes.
POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary
IDE channel is operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
Sub Class Code (SCC) — RO.
01h = IDE device, in the context of a mass storage device.
Base Class Code (BCC) — RO.
01 = Mass storage device
Cache Line Size (CLS) — RO.
00h = Hardwired. The IDE controller is implemented internally so this register has no
meaning.
8Ah
01h
01h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
ICH7 supports bus master operation
IDE Controller Registers (D31:F1)
Intel
RO, R/W
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
®
ICH7 Family Datasheet