NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 89
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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Intel
Table 3-4.
Intel
®
GPIO[15:12,10:8]
AZ_DOCK_RST# /
®
AZ_DOCK_EN# /
ICH7 Pin States
Signal Name
ACZ_BIT_CLK
ICH7 Family Datasheet
GPIO[28:26]
GPIO[39:37]
GPIO[7:6]
SPI_MOSI
SPI_CS#
SPI_ARB
SPI_CLK
GPIO34
GPIO33
GPIO18
GPIO19
GPIO24
GPIO25
Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 4 of 4)
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after
PLTRST#.
The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately
after RSMRST#.
In S3
and interfaces may be powered when the Intel
PETp/n[6:1] high until port is enabled by software.
LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3–S5 states
depending upon whether or not the LAN power planes are active.
SLP_S5# signals will be high in the S4 state.
The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled
or low if it is disabled.
ICH7 drives these signals High after the processor Reset.
CPUPWRGD is an output that represents a logical AND of the Intel
and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or
PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD
will be expected to transition from low to High.
IICH7 drives these signals Low before PWROK rising and Low after the processor Reset.
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Power
Plane
HOT
Core
Core
Core
Core
Core
Core
Core
, signal states are platform implementation specific, as some external components
PLTRST#
Internal Pull-
RSMRST#
High-Z with
No Change
During
down
Input
Input
Input
Input
High
Unmultiplexed GPIO Signals
High
High
High
High
Low
Low
Low
Low
SPI Interface (Mobile Only)
1
2
/
Immediately
PLTRST#
See Note 12
RSMRST#
No Change
High
Low
Low
after
Input
Input
Input
Input
High
High
High
Low
Low
Low
11
11
13
1
2
/
®
ICH7 is in the S3
Running
Defined
Defined
Defined
Defined
Defined
C3/C4
Driven
Driven
Driven
Driven
Driven
High
High
Low
Low
Defined
Defined
Defined
Defined
Defined
Driven
Driven
Driven
Driven
Driven
High
High
Low
Low
Low
S1
HOT
®
ICH7’s VRMPWRGD
state.
S3
Defined
Defined
Defined
Driven
High
High
Low
Low
COLD
Off
Off
Off
Off
Off
Off
Off
3
Driven
Define
Define
Define
High
High
S4/
Low
Low
Off
Off
Off
Off
Off
Off
Off
S5
d
d
d
89
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