NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 397

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.4.2
Intel
®
ICH7 Family Datasheet
ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller
Default Value:
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
7:5
Bit
4
3
2
1
0
ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.
000 = Should be programmed to “000”
ICW/OCW Select — WO.
1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4
sequence.
Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level
triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).
ADI — WO.
0 = Ignored for the Intel
Single or Cascade (SNGL) — WO.
0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.
ICW4 Write Required (IC4) — WO.
1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be
programmed.
Slave Controller
All bits undefined
®
ICH7. Should be programmed to 0.
–
–
A0h
20h
Description
Attribute:
Size:
WO
8 bit /controller
397