NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 61

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Signal Description
Table 2-8.
Intel
®
ICH7 Family Datasheet
IDE Interface Signals (Sheet 2 of 2)
WDMARDY#)
RDMARDY#)
DIOW# /
(DWSTB /
DIOR# /
IORDY /
(DRSTB /
DDACK#
(DSTOP)
DDREQ
Name
Type
O
O
O
I
I
IDE Device DMA Request: This input signal is directly driven from the
DRQ signal on the IDE connector. It is asserted by the IDE device to
request a data transfer, and used in conjunction with the PCI bus master
IDE function and are not associated with any AT compatible DMA
channel. There is a weak internal pull-down resistor on this signal.
IDE Device DMA Acknowledge: This signal directly drives the DAK#
signal on the IDE connector. DDACK# is asserted by the Intel
indicate to IDE DMA slave devices that a given data transfer cycle
(assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal
is used in conjunction with the PCI bus master IDE function and are not
associated with any AT-compatible DMA channel.
Disk I/O Read (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may drive data onto the DD lines. Data is latched
by the ICH7 on the deassertion edge of DIOR#. The IDE device is
selected either by the ATA register file chip selects (DCS1# or DCS3#)
and the DA lines, or the IDE DMA acknowledge (DDAK#).
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write
strobe for writes to disk. When writing to disk, ICH7 drives valid data on
rising and falling edges of DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for
reads from disk. When reading from disk, ICH7 deasserts RDMARDY# to
pause burst data transfers.
Disk I/O Write (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may latch data from the DD lines. Data is latched
by the IDE device on the deassertion edge of DIOW#. The IDE device is
selected either by the ATA register file chip selects (DCS1# or DCS3#)
and the DA lines, or the IDE DMA acknowledge (DDAK#).
Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst.
I/O Channel Ready (PIO): This signal will keep the strobe active
(DIOR# on reads, DIOW# on writes) longer than the minimum width. It
adds wait-states to PIO transfers.
Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
disk, ICH7 latches data on rising and falling edges of this signal from
the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this
is de-asserted by the disk to pause burst data transfers.
Description
®
ICH7 to
61