NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 479
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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UHCI Controllers Registers
11.2
Table 11-2. USB I/O Registers
Intel
®
ICH7 Family Datasheet
USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub
ports function such that on read back they reflect the current state of the port, and not
necessarily the state of the last write to the register. This allows the software to poll the
state of the port and wait until it is in the proper state before proceeding. A host
controller reset, global reset, or port reset will immediately terminate a transfer on the
affected ports and disable the port. This affects the USBCMD register, bit 4 and the
PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
NOTES:
1.
BASE +
00–01h
02–03h
04–05h
06–07h
08–0Bh
0D–0Fh
10–11h
12–13h
Offset
0Ch
These registers are WORD writable only. Byte writes to these registers have unpredictable
effects.
FRBASEADD
Mnemonic
USBINTR
PORTSC0
PORTSC1
SOFMOD
USBCMD
USBSTS
FRNUM
—
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Port 0 Status/Control
Port 1 Status/Control
Reserved
Register Name
Undefined
Default
0000h
0020h
0000h
0000h
0080h
0080h
40h
—
R/W (see Note 1)
R/WC, RO, R/W
R/WC, RO, R/W
(see Note 1)
(see Note 1)
R/WC
Type
R/W
R/W
R/W
R/W
—
479
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