NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 751

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
Intel
®
ICH7 Family Datasheet
Bit
2
1
0
Interrupt on Completion Enable — R/W.
0 = Disable.
1 = Enable. This bit controls whether or not an interrupt occurs when a buffer
Stream Run (RUN) — R/W.
0 = Disable. The DMA engine associated with this input stream will be disabled.
1 = Enable. The DMA engine associated with this input stream will be enabled to
Stream Reset (SRST) — R/W.
0 = Writing a 0 causes the corresponding stream to exit reset. When the stream
1 = Writing a 1 causes the corresponding stream to be reset. The Stream
completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the
Status register will be set, but the interrupt will not occur.
The hardware will report a 0 in this bit when the DMA engine is actually
stopped. Software must read a 0 from this bit before modifying related control
registers or restarting the DMA engine.
transfer data from the FIFO to the main memory. The SSYNC bit must also be
cleared in order for the DMA engine to run. For output streams, the cadence
generator is reset whenever the RUN bit is set.
hardware is ready to begin operation, it will report a 0 in this bit. Software
must read a 0 from this bit before accessing any of the stream registers.
Descriptor registers (except the SRST bit itself) and FIFO’s for the
corresponding stream are reset. After the stream hardware has completed
sequencing into the reset state, it will report a 1 in this bit. Software must
read a 1 from this bit to verify that the stream is in reset. The RUN bit must be
cleared before SRST is asserted.
Description
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