NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 308

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

8.1.8
8.1.9
8.1.10
308
CLS—Cache Line Size Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Ch
Default Value:
PMLT—Primary Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Dh
Default Value:
HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value:
7:5
4:3
2:0
7:3
2:0
6:0
Bit
Bit
Bit
7
Reserved
Cache Line Size (CLS) — R/W.
00 = Memory Write and Invalidate (MWI) command will not be used by the integrated
01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a
10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a
11 = Invalid. MWI command will not be used.
Reserved
Master Latency Timer Count (MLTC) — R/W. This field defines the number of PCI
clock cycles that the integrated LAN controller may own the bus while acting as bus
master.
Reserved
Multi-Function Device (MFD) — RO. Hardwired to 0 to indicate a single function device.
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space as an Ethernet controller.
LAN controller.
value of 08h is written to this register).
value of 10h is written to this register).
00h
00h
00h
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
R/W
8 bits
R/W
8 bits
RO
8 bits
®
ICH7 Family Datasheet