NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 145
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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Functional Description
5.11.5
Table 5-20. Data Frame Format
Intel
®
ICH7 Family Datasheet
Data Frame Format
Table 5-20
output from the ICH7 is ANDed with the PCI input signal. This way, the interrupt can be
signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are
shared).
Frame #
Data
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
shows the format of the data frames. For the PCI interrupts (A
PCI INTD#
PCI INTA#
PCI INTB#
PCI INTC#
Interrupt
IOCHCK#
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
SMI#
IRQ0
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
Clocks Past
Frame
Start
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
2
5
8
Ignored. IRQ0 can only be generated via the internal
8524
Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
Ignored. IRQ8# can only be generated internally.
Ignored. IRQ13 can only be generated from FERR#
Not attached to PATA or SATA logic
Not attached to PATA or SATA logic
Same as ISA IOCHCK# going active.
Drive PIRQA#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
Comment
–
D), the
145
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