NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 617

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1)
15.2.3
Intel
®
ICH7 Family Datasheet
BMIDP—Bus Master IDE Descriptor Table Pointer Register
(IDE—D31:F1)
Address Offset: BMIBASE + 04h
Default Value:
31:2
1:0
Bit
Bit
2
1
0
Address of Descriptor Table (ADDR) — R/W. Corresponds to A[31:2]. The
Descriptor Table must be DWord-aligned. The Descriptor Table must not cross a 64-K
boundary in memory.
Reserved
Interrupt — R/WC. Software can use this bit to determine if an IDE device has
asserted its interrupt line (IDEIRQ).
0 = Software clears this bit by writing a 1 to it. If this bit is cleared while the
1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH7 when the last transfer for a region is performed,
1 = Set by the ICH7 when the Start bit is written to the Command register.
interrupt is still active, this bit will remain clear until another assertion edge is
detected on the interrupt line.
interrupt is masked in the 8259 or the internal I/O APIC. When this bit is read as
1, all data transferred from the drive is visible in system memory.
when transferring data on PCI.
where EOT for that region is set in the region descriptor. It is also cleared by the
ICH7 when the Start bit is cleared in the Command register. When this bit is read
as 0, all data transferred from the drive during the previous bus master
command is visible in system memory, unless the bus master command was
aborted.
All bits undefined
§
Description
Description
Attribute:
Size:
R/W
32 bits
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