NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 391

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.2.8
10.2.9
10.2.10
Intel
®
ICH7 Family Datasheet
DMA Clear Byte Pointer Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
DMA Master Clear Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
7:0
Bit
7:0
7:0
Bit
Bit
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the
I/O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
Master Clear — WO. No specific pattern. Enabled with a write to the port. This has the
same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
Clear Mask Register — WO. No specific pattern. Command enabled with a write to the
port.
Ch. #0
Ch. #4
xxxx xxxx
No
Ch. #0
Ch. #4
xxxx xxxx
Ch. #0
Ch. #4
xxxx xxxx
No
–
–
–
–
–
–
3 = 0Ch;
7 = D8h
3 = 0Dh;
7 = DAh
3 = 0Eh;
7 = DCh
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Attribute:
Size:
Power Well:
WO
8-bit
Core
WO
8-bit
WO
8-bit
Core
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