NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 635

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.2.1
16.2.2
Intel
®
ICH7 Family Datasheet
x_BDBAR—Buffer Descriptor Base Address Register
(Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single 32-bit read from
address offset 00h. Reads across DWord boundaries are not supported.
x_CIV—Current Index Value Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software can also read this
register individually by doing a single, 8-bit read to offset 04h.
NOTE: Reads across DWord boundaries are not supported.
31:3
2:0
7:5
4:0
Bit
Bit
Buffer Descriptor Base Address[31:3] — R/W. These bits represent address bits
31:3. The data should be aligned on 8-byte boundaries. Each buffer descriptor is 8
bytes long and the list can contain a maximum of 32 entries.
Hardwired to 0.
Hardwired to 0
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within
the list of 32 descriptors is currently being processed. As each descriptor is processed,
this value is incremented. The value rolls over after it reaches 31.
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
00000000h
No
NABMBAR + 04h (PICIV),
NABMBAR + 14h (POCIV),
NABMBAR + 24h (MCCIV)
MBBAR + 44h (MC2CIV)
MBBAR + 54h (PI2CIV)
MBBAR + 64h (SPCIV)
00h
No
Description
Description
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
32 bits
Core
RO
8 bits
Core
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