NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 186

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Figure 5-8.
5.16.2.2
5.16.2.3
Note:
Note:
186
Physical Region Descriptor Table Entry
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO
transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to
program fast timing mode for DMA transactions only. This is useful for IDE devices
whose DMA transfer timings are faster than its PIO transfer timings. The IDE device
DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is
deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI
clock and no more transfers take place until DMA request is asserted again.
Interrupts
The ICH7 can generate interrupts based upon a signal coming from the PATA device, or
due to the completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and
active high. The PATA host controller generates IDEIRQ.
When the ICH7 IDE controller is operating independently from the SATA controller
(D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA
controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in
turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV
(D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is
emulating the logical secondary channel (MAP.MV = 1h), the PATA channel will emulate
the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA
controller in combined mode is emulating the logical primary channel (MAP.MV=2h),
IDEIRQ will generate IRQ15.
IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.
The combined mode is not supported on ICH7-U Ultra Mobile. ICH7-U does not contain
a SATA controller.
EOT
Byte 3
Memory Region Physical Base Address [31:1]
Reserved
Byte 2
Byte 1
Byte Count [15:1]
Byte 0
o
o
Intel
®
ICH7 Family Datasheet
Functional Description
Main Memory
Memory
Region