NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 417
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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Compliant
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LPC Interface Bridge Registers (D31:F0)
10.7.4
10.7.5
Intel
®
ICH7 Family Datasheet
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
RST_CNT—Reset Control Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bits
7:0
7:4
Bit
3
2
1
0
Coprocessor Error (COPROC_ERR) — R/W. Any value written to this register will
cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to
generate an internal IRQ13, the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0,
Bit 13) must be 1. Reads to this register always return 00h.
Reserved
Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#,
SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),
after PWROK going low (with RSMRST# high), or after two TCO timeouts.
0 = Intel
1 = ICH7 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)
Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a
hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to
the processor.
0 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a soft reset by activating
1 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a hard reset by activating
Reserved
INIT# for 16 PCI clocks.
PLTRST# and SUS_STAT# active for about 5-6 milliseconds, however the
SLP_S3#, SLP_S4# and SLP_S5# will NOT go active. The ICH7 main power well is
reset when this bit is 1. It also resets the resume well bits (except for those noted
throughout the datasheet).
in response to SYSRESET#, PWROK#, and Watchdog timer reset sources.
®
F0h
00h
No
CF9h
00h
No
ICH7 will keep SLP_S3#, SLP_S4# and SLP_S5# high.
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
8-bits
Core
R/W
8-bit
Core
417
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