NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 321
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.5
Intel
®
ICH7 Family Datasheet
EEPROM_CNTL—EEPROM Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value:
The EEPROM Control Register is a 16-bit field that enables a read from and a write to
the external EEPROM.
7:4
Bit
3
2
1
0
Reserved
EEPROM Serial Data Out (EEDO) — RO. Note that this bit represents “Data Out”
from the perspective of the EEPROM device. This bit contains the value read from the
EEPROM when performing read operations.
EEPROM Serial Data In (EEDI) — WO. Note that this bit represents “Data In” from
the perspective of the EEPROM device. The value of this bit is written to the EEPROM
when performing write operations.
EEPROM Chip Select (EECS) — R/W.
0 = Drives the Intel
1 = Drives the ICH7’s EE_CS signal high, to enable the EEPROM.
EEPROM Serial Clock (EESK) — R/W. Toggling this bit clocks data into or out of the
EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM
component’s minimum clock frequency specification.
0 = Drives the ICH7’s EE_SHCLK signal low.
1 = Drives the ICH7’s EE_SHCLK signal high.
set to 0 for a minimum of 1 μs between consecutive instruction cycles.
00h
®
ICH7’s EE_CS signal low to disable the EEPROM. this bit must be
Description
Attribute:
Size:
RO, R/W, WO
8 bits
321
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