NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 300

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

300
13:12
Bit
15
14
11
10
9
8
7
6
5
4
3
EHCI Disable (EHCID) — R/W.
0 = The EHCI is enabled. (Default)
1 = The EHCI is disabled.
LPC Bridge Disable (LBD) — R/W.
0 = The LPC bridge is enabled. (Default)
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following
Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is
set, but the aliases at the top of 1 MB (the E and F segment) no longer will be
decoded.
Reserved
UHCI #4 Disable (U4D) — R/W.
0 = The 4th UHCI (ports 6 and 7) is enabled. (Default)
1 = The 4th UHCI (ports 6 and 7) is disabled.
UHCI #3 Disable (U3D) — R/W.
0 = The 3rd UHCI (ports 4 and 5) is enabled. (Default)
1 = The 3rd UHCI (ports 4 and 5) is disabled.
UHCI #2 Disable (U2D) — R/W.
0 = The 2nd UHCI (ports 2 and 3) is enabled. (Default)
1 = The 2nd UHCI (ports 2 and 3) is disabled.
UHCI #1 Disable (U1D) — R/W.
0 = The 1st UHCI (ports 0 and 1) is enabled. (Default)
1 = The 1st UHCI (ports 0 and 1) is disabled.
Hide Internal LAN (HIL) — R/W.
0 = The LAN controller is enabled. (Default)
1 = The LAN controller is disabled and will not decode configuration cycles off of PCI
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. .
AC ‘97 Modem Disable (AMD) — R/W.
0 = The AC ‘97 modem function is enabled. (Default)
1 = The AC ‘97 modem function is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
AC ‘97 Audio Disable (AAD) — R/W.
0 = The AC ‘97 audio function is enabled. (Default)
1 = The AC ‘97 audio function is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
Intel
0 = The Intel High Definition Audio controller is enabled. (Default)
1 = The Intel High Definition Audio controller is disabled and its PCI configuration
SM Bus Disable (SD) — R/W.
0 = The SM Bus controller is enabled. (Default)
1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the I/
• Memory cycles below 16 MB (1000000h)
• I/O cycles below 64 KB (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
additional spaces will no longer be decoded by the LPC bridge:
space is not accessible.
O space. In the Intel
®
High Definition Audio Disable (ZD) — R/W.
®
ICH7, it only disables the configuration space.
Description
Chipset Configuration Registers
Intel
®
ICH7 Family Datasheet