NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 278

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

7.1.34
278
RPC—Root Port Configuration Register
Offset Address: 0224–0227h
Default Value:
31:8
6:4
1:0
Bit
7
3
2
Reserved
High Priority Port Enable (HPE) — R/W.
0 = The high priority path is not enabled.
1 = The port selected by the HPP field in this register is enabled for high priority. It
High Priority Port (HPP) — R/W. This field controls which port is enabled for high
priority when the HPE bit in this register is set.
111 = Reserved
110 = Reserved
101 = Port 6
100 = Port 5
100 = Port 4
010 = Port 3
001 = Port 2
000 = Port 1
Reserved
Port Configuration2 (PC2) — RO. This bit controls how the PCI bridges are
organized in various modes of operation for Ports 5 and 6.
1 = Reserved
0 = 2 x1s, Port 5 (x1), Port 6 (x1)
This bit is in the resume well and is only reset by RSMRST#.
Port Configuration (PC) — RO. This field controls how the PCI bridges are
organized in various modes of operation. For the following mappings, if a port is not
shown, it is considered a x1 port with no connection.
These bits represent the strap values of ACZ_SDOUT (bit 1) and ACZ_SYNC (bit 0)
when TP3 is not pulled low at the rising edge of PWROK.
11 = 1 x4, Port 1 (x4)
10 = Reserved
01 = Reserved
00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1)
These bits live in the resume well and are only reset by RSMRST#.
will be arbitrated above all other VC0 (including integrated VC0) devices.
0000000yh (y = 00xxb)
Description
Attribute:
Size:
Chipset Configuration Registers
Intel
R/W, RO
32-bit
®
ICH7 Family Datasheet