NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 461

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.9.7
10.9.8
Intel
®
ICH7 Family Datasheet
TCO2_CNT—TCO2 Control Register
I/O Address:
Default Value:
Lockable:
TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address:
Default Value:
Lockable:
15:6
5:4
2:1
7:0
Bit
Bit
3
0
Reserved
OS_POLICY — R/W. OS-based software writes to these bits to select the policy that
the BIOS will use after the platform resets due the WDT. The following convention is
recommended for the BIOS and OS:
00 = Boot normally
01 = Shut down
10 = Don’t load OS. Hold in pre-boot state and use LAN to determine next step
11 = Reserved
NOTE: These are just scratchpad bits. They should not be reset when the TCO logic
GPIO11_ALERT_DISABLE — R/W. At reset (via RSMRST# asserted) this bit is set
and GPIO11 alerts are disabled.
0 = Enable.
1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus
INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes
active.
00 = No interrupt or SMI#
01 = Interrupt (as selected by TCO_INT_SEL).
10 = SMI
11 = Reserved
Reserved
TCO_MESSAGE[n] — R/W. The value written into this register will be sent out via the
SMLINK interface in the MESSAGE field of the Alert On LAN message. BIOS can write to
this register to indicate its boot progress which can be monitored externally.
slave.
resets the platform due to Watchdog Timer.
TCOBASE +0Ah
0008h
No
TCOBASE +0Ch (Message 1)
TCOBASE +0Dh (Message 2)
00h
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well: Resume
R/W
16-bit
Resume
R/W
8-bit
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