NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 40
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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Table 1-1.
40
Industry Specifications
Chapter 1. Introduction
Chapter 1
gives a general overview of the ICH7.
Chapter 2. Signal Description
Chapter 2
description of each signal. Signals are arranged according to interface and details are
provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals.
Chapter 3. Intel
Chapter 3
level in each suspend state, and their logic level before and after reset.
Chapter 4. Intel
Chapter 4
based system.
Chapter 5. Functional Description
Chapter 5
devices and functions in this manual are abbreviated using the following nomenclature;
Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8,
D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For
example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is
abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be
considered to be Bus 0. Note that the ICH7’s external PCI bus is typically Bus 1, but
may be assigned a different number depending upon system configuration.
System Management Bus Specification, Version 2.0
(SMBus)
PCI Local Bus Specification, Revision 2.3 (PCI)
PCI Mobile Design Guide, Revision 1.1
PCI Power Management Specification, Revision 1.1
Universal Serial Bus Specification (USB), Revision 2.0
Advanced Configuration and Power Interface, Version
2.0 (ACPI)
Universal Host Controller Interface, Revision 1.1 (UHCI)
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
Serial ATA Specification, Revision 1.0a
Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0
Alert Standard Format Specification, Version 1.03
IEEE 802.3 Fast Ethernet
AT Attachment - 6 with Packet Interface (ATA/ATAPI -
6)
IA-PC HPET (High Precision Event Timers) Specification,
Revision 1.0
introduces the ICH7 and provides information on manual organization and
provides a block diagram of the ICH7 interface signals and a detailed
provides a complete list of signals, their associated power well, their logic
provides a list of each clock domain associated with the ICH7 in an ICH7
provides a detailed description of the functions in the ICH7. All PCI buses,
®
®
Specification
ICH7 Pin States
ICH7 and System Clock Domains
http://www.smbus.org/specs/
http://www.pcisig.com/specifications
http://www.pcisig.com/specifications
http://www.pcisig.com/specifications
http://www.usb.org/developers/docs
http://www.acpi.info/spec.htm
http://developer.intel.com/design/
USB/UHCI11D.htm
http://developer.intel.com/
technology/usb/ehcispec.htm
http://www.serialata.org/
specifications.asp
http://www.serialata.org/
specifications.asp
http://www.dmtf.org/standards/asf
http://standards.ieee.org/
getieee802/
http://T13.org (T13 1410D)
http://www.intel.com/
hardwaredesign/hpetspec.htm
Intel
Location
®
ICH7 Family Datasheet
Introduction
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