NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 238

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Note:
5.22.3.1
Figure 5-16. SDIN Wake Signaling
238
ACZ_BIT_CLK and ACZ_SDIN transition low immediately after a write to the
Powerdown Register (26h) with PR4 enabled. When the AC ’97 controller driver is at the
point where it is ready to program the AC-link into its low-power mode, slots 1 and 2
are assumed to be the only valid stream in the audio output frame.
The AC ’97 controller also drives ACZ_SYNC, and ACZ_SDOUT low after programming
AC ’97 to this low power, halted mode
Once the codec has been instructed to halt, ACZ_BIT_CLK, a special wake up protocol
must be used to bring the AC-link to the active mode since normal output and input
frames can not be communicated in the absence of ACZ_BIT_CLK. Once in a low-power
mode, the ICH7 provides three methods for waking up the AC-link; external wake
event, cold reset and warm reset.
Before entering any low-power mode where the link interface to the codec is expected
to be powered down while the rest of the system is awake, the software must set the
“Shut Off” bit in the control register.
External Wake Event
Codecs can signal the controller to wake the AC-link, and wake the system using
ACZ_SDIN.
The minimum ACZ_SDIN wake up pulse width is 1 us. The rising edge of ACZ_SDIN0,
ACZ_SDIN1 or ACZ_SDIN2 causes the ICH7 to sequence through an AC-link warm
reset and set the AC97_STS bit in the GPE0_STS register to wake the system. The
primary codec must wait to sample ACZ_SYNC high and low before restarting
ACZ_BIT_CLK as diagrammed in
must keep its ACZ_SDIN high until it has sampled ACZ_SYNC having gone high, and
then low.
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used
depends on the system’s current power down state. Unless a cold or register reset (a
write to the Reset register in the codec) is performed, wherein the AC ’97 codec
registers are initialized to their default values, registers are required to keep state
during all power down modes.
Once powered down, activation of the AC-link via re-assertion of the ACZ_SYNC signal
must not occur for a minimum of four audio frame times following the frame in which
the power down was triggered. When AC-link powers up, it indicates readiness via the
codec ready bit.
BIT_CLK
SDOUT
SDIN
SYNC
prev. frame
prev. frame
slot 12
slot 12
TAG
TAG
Power Down
Write to
Frame
0x20
Data
PR4
Figure
Sleep State
5-16. The codec that signaled the wake event
Wake Event
Intel
®
ICH7 Family Datasheet
Functional Description
TAG
TAG
New Audio
Frame
Slot 1
Slot 1
Slot 2
Slot 2