NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 172
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
- Current page: 172 of 848
- Download datasheet (7Mb)
Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
172
Addr
I/O
08h
20h
# of
Rds
12
6
NOTES:
1.
2.
Access
10
11
12
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
Restore Data
Bits 5, 3, 1, and 0 return 0.
The OCW1 register must be read before entering ALT access mode.
DMA Chan 0–3 Command
DMA Chan 0–3 Request
DMA Chan 0 Mode:
Bits(1:0) = 00
DMA Chan 1 Mode:
Bits(1:0) = 01
DMA Chan 2 Mode:
Bits(1:0) = 10
DMA Chan 3 Mode: Bits(1:0)
= 11.
PIC ICW2 of Master controller
PIC ICW3 of Master controller
PIC ICW4 of Master controller
PIC OCW1 of Master
controller
PIC OCW2 of Master controller
PIC OCW3 of Master controller
PIC ICW2 of Slave controller
PIC ICW3 of Slave controller
PIC ICW4 of Slave controller
PIC OCW1 of Slave controller
PIC OCW2 of Slave controller
PIC OCW3 of Slave controller
2
Data
2
1
Addr
I/O
CCh
D0h
CAh
CEh
# of
Rds
2
2
2
6
Access
1
2
1
2
1
2
1
2
3
4
5
6
Restore Data
DMA Chan 6 base count low
byte
DMA Chan 6 base count high
byte
DMA Chan 7 base address low
byte
DMA Chan 7 base address
high byte
DMA Chan 7 base count low
byte
DMA Chan 7 base count high
byte
DMA Chan 4–7 Command
DMA Chan 4–7 Request
DMA Chan 4 Mode: Bits(1:0)
= 00
DMA Chan 5 Mode: Bits(1:0)
= 01
DMA Chan 6 Mode: Bits(1:0)
= 10
DMA Chan 7 Mode: Bits(1:0)
= 11.
Intel
®
ICH7 Family Datasheet
Functional Description
Data
1
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