NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 575

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
Intel
®
ICH7 Family Datasheet
11:10
Bit
12
9
8
7
Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does
have power.
Line Status— RO.These bits reflect the current logical levels of the D+ (bit 11) and D–
(bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to
the port reset and enable sequence. This field is valid only when the port enable bit is 0
and the current connect status bit is set to a 1.
00 = SE0
10 = J-state
01 = K-state
11 = Undefined
Reserved. This bit will return a 0 when read.
Port Reset — R/W. Default = 0. When software writes a 1 to this bit (from a 0), the
bus reset sequence as defined in the USB Specification, Revision 2.0 is started.
Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep
this bit at a 1 long enough to ensure the reset sequence completes as specified in the
USB Specification, Revision 2.0.
1 = Port is in Reset.
0 = Port is not in Reset.
NOTE: When software writes a 0 to this bit, there may be a delay before the bit status
NOTE: System software should not attempt to reset a port if the HCHalted bit in the
Suspend — R/W.
0 = Port not in suspend state.(Default)
1 = Port in suspend state.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
When in suspend state, downstream propagation of data is blocked on this port, except
for port reset. Note that the bit status does not change until the port is suspended and
that there may be a delay in suspending a port depending on the activity on the port.
The host controller will unconditionally set this bit to a 0 when software sets the Force
Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host
controller.
If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is
a 0) the results are undefined.
Port Enabled
changes to a 0. The bit status will not read as a 0 until after the reset has
completed. If the port is in high-speed mode after reset is complete, the host
controller will automatically enable this port (e.g., set the Port Enable bit to a
1). A host controller must terminate the reset and stabilize the state of the port
within 2 milliseconds of software transitioning this bit from 0 to 1.
For example: if the port detects that the attached device is high-speed during
reset, then the host controller must have the port in the enabled state within
2 ms of software writing this bit to a 0. The HCHalted bit (D29:F7:CAPLENGTH
+ 24h, bit 12) in the USB2.0_STS register should be a 0 before software
attempts to use this bit. The host controller may hold Port Reset asserted to a 1
when the HCHalted bit is a 1. This bit is 0 if Port Power is 0
USB2.0_STS register is a 1. Doing so will result in undefined behavior.
0
1
1
Suspend
X
0
1
Description
Port State
Disabled
Suspend
Enabled
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