876784 Intel, 876784 Datasheet - Page 109

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.3.1.1
Intel
®
ICH7 Family Datasheet
Bus Slave Operation
The ICH7 integrated LAN controller serves as a target device in one of the following
cases:
The size of the CSR memory space is 4 Kbyte in the memory space and 64 bytes in the
I/O space. The LAN controller treats accesses to these memory spaces differently.
Control/Status Register (CSR) Accesses
The integrated LAN controller supports zero wait-state single cycle memory or I/O
mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and
64 bytes of I/O space to accomplish this. Based on its needs, the software driver uses
either memory or I/O mapping to access these registers. The LAN controller provides
four valid KB of CSR space that include the following elements:
In the case of accessing the Control/Status Registers, the processor is the initiator and
the LAN controller is the target.
Retry Premature Accesses
The LAN controller responds with a Retry to any configuration cycle accessing the LAN
controller before the completion of the automatic read of the EEPROM. The LAN
controller may continue to Retry any configuration accesses until the EEPROM read is
complete. The LAN controller does not enforce the rule that the retried master must
attempt to access the same address again in order to complete any delayed
transaction. Any master access to the LAN controller after the completion of the
EEPROM read is honored.
Error Handling
Data Parity Errors: The LAN controller checks for data parity errors while it is the
target of the transaction. If an error was detected, the LAN controller sets the Detected
Parity Error bit in the PCI Configuration Status register, bit 15. The LAN controller also
asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command
register, bit 6). The LAN controller does not attempt to terminate a cycle in which a
parity error was detected. This gives the initiator the option of recovery.
Target-Disconnect: The LAN controller prematurely terminate a cycle in the following
cases:
• Processor accesses to the LAN controller System Control Block (SCB) Control/
• Processor accesses to the EEPROM through its CSR
• Processor accesses to the LAN controller PORT address via the CSR
• Processor accesses to the MDI control register in the CSR
• System Control Block (SCB) registers
• PORT register
• EEPROM control register
• MDI control register
• Flow control registers
• After accesses to its CSR
• After accesses to the configuration space
Status Registers (CSR)
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