876784 Intel, 876784 Datasheet - Page 478

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

11.1.18
11.1.19
478
USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
CWP—Core Well Policy Register
(USB—D29:F0/F1/F2/F3)
Address Offset: C8h
Default Value:
7:2
7:1
Bit
Bit
1
0
0
Reserved
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/
Reserved
Static Bus Master Status Policy Enable (SBMSPE) — R/W.
0 = The UHCI host controller dynamically sets the Bus Master status bit (Power
1 = The UHCI host controller statically forces the Bus Master Status bit in power
NOTE: The PCI Power Management registers are enabled in the PCI Device 31:
disconnect events.
disconnect events.
Management 1 Status Register,[PMBASE+00h], bit 4) based on the memory
accesses that are scheduled. For mobile/Ultra Mobile only, the default setting
provides a more accurate indication of snoopable memory accesses in order to help
with software-invoked entry to C3 and C4 power states.
management space to 1 whenever the HCHalted bit (USB Status Register,
Base+02h, bit 5) is cleared.
Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte
aligned).
00h
C4h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
R/W
8 bits
R/W
8 bits
UHCI Controllers Registers
®
ICH7 Family Datasheet